The demands of increasingly complex circuits continue to drive the development of engineered substrates. The Soitec Group’s ability to leverage Smart Cut™ technology, expertise in epitaxy and new layer transfer technologies offers tremendous potential.
A simple yet elegant solution, SOI was one of the first forms of engineered substrates. It is a stack of materials comprised of: the top “active” layer of high-quality silicon; a buried layer of electrically insulating silicon dioxide (“BOX”); and a bulk silicon mechanical support (the “handle”).
In more advanced forms of engineered substrates, the layers can be optimally tailored to the application.
With the focus on CMOS technologies for both high performance and low power silicon technologies, the ITRS roadmap calls for improved charge carrier mobilities. Several substrate level solutions are enabling candidates: the introduction of strained silicon, crystal orientation engineering and migration towards other high mobility semiconductors (Ge, III-V). For non-CMOS applications, migration to other active materials including III-V semiconductors (GaAs, InP, GaN) enable the industry to leverage engineered substrates in a broader domain, including RF and microwave devices, LEDs, lasers and more.
The buried layer can be tailored to vary thickness and more. Depending on the application, a more complex buried layer may improve thermal management and radiation hardness, for example, or act as an etch stop layer. Other insulating materials can be introduced (Si3N4 instead of the usual SiO2, for instance), and the structure itself can be customized (such as engineering stacks of different insulators).
For some applications, new materials for the handle wafer may be better suited than bulk silicon. Options pertaining to transparency, resistivity and thermal conductivity are of interest for fields like displays, RF and power applications.
Complex structures can be built by multiplying the levels of active layers and/or introducing patterned layers, opening doors for heterogeneous integration or System-On-Chip.
